US 12,431,609 B2
RFID tag and manufacturing method thereof
Takuro Shimada, Ehime (JP); and Alina Kan, Ehime (JP)
Assigned to Daio Paper Corporation, Ehime (JP)
Appl. No. 18/250,078
Filed by DAIO PAPER CORPORATION, Ehime (JP)
PCT Filed Dec. 13, 2021, PCT No. PCT/JP2021/045844
§ 371(c)(1), (2) Date Apr. 21, 2023,
PCT Pub. No. WO2022/131215, PCT Pub. Date Jun. 23, 2022.
Claims priority of application No. 2020-209378 (JP), filed on Dec. 17, 2020.
Prior Publication US 2023/0395966 A1, Dec. 7, 2023
Int. Cl. H01Q 1/22 (2006.01); G06K 19/077 (2006.01); H01Q 9/28 (2006.01)
CPC H01Q 1/2225 (2013.01) [G06K 19/07749 (2013.01); G06K 19/07773 (2013.01); G06K 19/07786 (2013.01); G06K 19/07794 (2013.01); H01Q 9/285 (2013.01); G06K 19/07756 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An RFID tag comprising:
a base material having a main surface; and
an inlay provided with an IC chip and an antenna on the base material,
wherein:
the antenna includes a loop conductive portion having both end portions connected to the IC chip so as to form a loop shape through the IC chip, and a dipole antenna portion disposed to surround the loop conductive portion with an interval allowing inductive coupling;
the loop conductive portion extends through the IC chip to form an oval shape or a substantially rectangular shape having a relatively short first axis of symmetry and a relatively long second axis of symmetry orthogonal thereto;
the IC chip is disposed at one end portion of the first axis of symmetry; and
the loop conductive portion and the dipole antenna portion are formed on the main surface to have a same thickness, and the IC chip is disposed on the both end portions of the loop conductive portion, characterized in that:
the dipole antenna portion is disposed to substantially surround the loop conductive portion at a certain interval; and
the dipole antenna portion has an axis of symmetry overlapping the first axis of symmetry, terminates at a pair of tip edges facing and spaced apart from each other with a virtual line obtained by extending an IC chip side of the first axis of symmetry interposed therebetween, and continues so as to wrap around the loop conductive portion from one side to the other side of each of the tip edges.