| CPC H01L 25/074 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H10D 30/798 (2025.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/13091 (2013.01)] | 14 Claims |
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14. A stacked semiconductor device comprising:
a lower semiconductor device comprising a lower interconnect that has first tapered sidewalls; and
a flipped upper semiconductor device comprising an upper interconnect that has second tapered sidewalls oppositely tapered relative to the first tapered sidewalls, the flipped upper semiconductor device bonded to the lower semiconductor device, the flipped upper semiconductor device comprising a flipped transistor comprising a source and a drain, an upper channel connected to the source and to the drain, a gate connected to the upper channel, a gate spacer between the gate and the source and between the gate and the drain, and a stressed dielectric portion directly upon the upper channel that imparts an intrinsic strain within the upper channel, wherein sidewalls of the stressed dielectric portion are vertically aligned with the gate spacer therebelow between the gate and the source and the gate and the drain.
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