US 12,431,448 B2
Semiconductor device
Tohru Shirakawa, Matsumoto (JP); Yasunori Agata, Matsumoto (JP); Naoki Saegusa, Matsumoto (JP); and Kaname Mitsuzuka, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Aug. 17, 2022, as Appl. No. 17/890,261.
Application 17/890,261 is a continuation of application No. PCT/JP2021/014967, filed on Apr. 8, 2021.
Claims priority of application No. 2020-152944 (JP), filed on Sep. 11, 2020.
Prior Publication US 2022/0392815 A1, Dec. 8, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/66 (2006.01); H10D 64/23 (2025.01); H01L 23/29 (2006.01); H10D 12/00 (2025.01); H10D 62/83 (2025.01); H10D 64/62 (2025.01)
CPC H01L 24/05 (2013.01) [H01L 22/32 (2013.01); H01L 24/06 (2013.01); H10D 64/231 (2025.01); H01L 23/296 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05012 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05019 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/0615 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/0715 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/186 (2013.01); H10D 12/481 (2025.01); H10D 62/83 (2025.01); H10D 64/62 (2025.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a semiconductor substrate, the semiconductor device comprising:
one or more sensing portions that are provided on the semiconductor substrate and that are configured to detect predetermined physical information;
one or more sensing pad portions provided above an upper surface of the semiconductor substrate and that is connected to a corresponding one of the one or more sensing portions;
a gate runner which is provided above the upper surface of the semiconductor substrate and to which a gate potential is applied; and
one or more separated conductive portions in which each separated conductive portion is provided between a corresponding one of the one or more sensing pad portions and the semiconductor substrate, wherein each of the one or more separated conductive portions is separated from the gate runner, wherein each of the one or more sensing pad portions has a connection region on an upper surface thereof, wherein the connection region is configured for the connection of a corresponding wire wiring portion, wherein at least one of the one or more separated conductive portions overlaps the connection region of the corresponding one of the one or more sensing pad portions in a top plan view.