US 12,431,446 B2
Package structure
Chih-Hsuan Tai, Taipei (TW); Ting-Ting Kuo, Hsinchu (TW); Yu-Chih Huang, Hsinchu (TW); Chih-Wei Lin, Hsinchu County (TW); Hsiu-Jen Lin, Hsinchu County (TW); Chih-Hua Chen, Hsinchu County (TW); Ming-Da Cheng, Taoyuan (TW); Ching-Hua Hsieh, Hsinchu (TW); Hao-Yi Tsai, Hsinchu (TW); and Chung-Shi Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on May 6, 2024, as Appl. No. 18/655,596.
Application 16/888,758 is a division of application No. 15/726,260, filed on Oct. 5, 2017, granted, now 10,672,729, issued on Jun. 2, 2020.
Application 18/655,596 is a continuation of application No. 17/670,481, filed on Feb. 13, 2022, granted, now 12,009,322.
Application 17/670,481 is a continuation of application No. 16/888,758, filed on May 31, 2020, granted, now 11,251,141, issued on Feb. 15, 2022.
Claims priority of provisional application 62/479,223, filed on Mar. 30, 2017.
Prior Publication US 2024/0290734 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01)
CPC H01L 24/02 (2013.01) [H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02319 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/12105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a semiconductor device;
a molding compound surrounding the semiconductor device;
a dielectric layer over the semiconductor device and the molding compound;
a redistribution line over the dielectric layer;
a first via extending from a bottom surface of the redistribution line to below a bottom surface of the molding compound, wherein an interface between the redistribution line and the first via is higher than a top surface of the molding compound and lower than an interface between the redistribution line and the dielectric layer; and
a second via extending from the bottom surface of the redistribution line to a conductive pad of the semiconductor device.