| CPC H01L 23/535 (2013.01) [H01L 21/0259 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
active regions extending in a first direction on a substrate;
a gate electrode intersecting the active regions on the substrate and extending in a second direction;
first and second channel structures spaced apart from each other in the second direction on the active regions, each of the first and second channel structures including a plurality of channel layers spaced apart from each other in a third direction perpendicular to an upper surface of the substrate and surrounded by the gate electrode;
an interconnection line on the gate electrode and connected to the gate electrode; and
source/drain regions in regions in which the active regions are recessed on both sides of the gate electrode and in contact with the plurality of channel layers,
the gate electrode including a contact region located on at least a portion of a first uppermost channel layer that is an uppermost channel layer among the plurality of channel layers of the first channel structure and connected to the interconnection line, and
the gate electrode exposing at least a portion of a second uppermost channel layer that is an uppermost channel layer among the plurality of channel layers of the second channel structure.
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