US 12,431,432 B2
Method and apparatus for supplying power to VLSI silicon chips
Hassan Naser, Austin, TX (US); and Daniel Stasiak, Austin, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,344.
Application 17/556,344 is a division of application No. 16/134,269, filed on Sep. 18, 2018, granted, now 11,205,620.
Prior Publication US 2022/0115325 A1, Apr. 14, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/495 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 24/73 (2013.01); H01L 23/3677 (2013.01); H01L 23/49582 (2013.01); H01L 2224/73257 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of providing power and signals to an integrated circuit, the method comprising:
providing one or more signals to one or more front-side metal signal layers formed above a top surface of a silicon substrate, wherein circuitry is formed in the top surface of the silicon substrate that has one or more transistors;
providing one or more power voltages to one or more back-side metal layers formed below a bottom surface of the silicon substrate; and
providing the one or more power voltages from the one or more back-side metal layers to one or more through silicon vias (TSVs) formed through the silicon substrate and routing the one or more power voltages from the one or more TSVs through the silicon substrate to one or more front-side metal power voltage layers formed above the top surface of the silicon substrate.