US 12,431,424 B2
Buried power rails integrated with decoupling capacitance
Bernd Waidhas, Pettendorf (DE); Harald Gossner, Riemerling (DE); Wolfgang Molzer, Ottobrunn (DE); Georg Seidemann, Landshut (DE); Michael Langenbuch, Munich (DE); Martin Ostermayr, Woerth (DE); Joachim Singer, Munich (DE); Thomas Wagner, Regelsbach (DE); and Klaus Herold, Munich (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 17, 2021, as Appl. No. 17/554,112.
Prior Publication US 2023/0197599 A1, Jun. 22, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H01L 23/5226 (2013.01) [H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a support structure having a first surface and a second surface opposing the first surface;
a first layer comprising at least a portion of a transistor and adjoining the first surface;
a first buried power rail and a second buried power rail that are at least partially buried in the support structure and coupled to the transistor; and
a second layer comprising a capacitor and adjoining the second surface, the capacitor including:
a first capacitor electrode comprising a group of first conductive fingers,
a second capacitor electrode comprising a group of second conductive fingers, and
a capacitor insulator between the first capacitor electrode and the second capacitor electrode,
wherein individual first conductive fingers alternate with individual second conductive fingers, the capacitor insulator is between an individual first conductive finger and an individual second conductive finger, the first capacitor electrode is coupled to the first buried power rail, and the second capacitor electrode is coupled to the second buried power rail.