US 12,431,412 B2
Contact plugs for semiconductor device and method of forming same
Mrunal A. Khaderbad, Hsinchu (TW); Yasutoshi Okuno, Hsinchu (TW); Sung-Li Wang, Zhubei (TW); Pang-Yen Tsai, Jhubei (TW); Shen-Nan Lee, Jhudong Township (TW); and Teng-Chun Tsai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/356,031.
Application 18/356,031 is a continuation of application No. 17/101,158, filed on Nov. 23, 2020, granted, now 11,756,864.
Application 17/101,158 is a continuation of application No. 16/112,122, filed on Aug. 24, 2018, granted, now 10,847,413, issued on Nov. 24, 2020.
Claims priority of provisional application 62/592,714, filed on Nov. 30, 2017.
Prior Publication US 2024/0021501 A1, Jan. 18, 2024
Int. Cl. H10D 30/01 (2025.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 64/20 (2025.01); H10D 64/23 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H01L 23/485 (2013.01) [H01L 21/02634 (2013.01); H01L 21/28562 (2013.01); H01L 21/31116 (2013.01); H01L 21/76814 (2013.01); H01L 21/76822 (2013.01); H01L 21/76826 (2013.01); H01L 21/76831 (2013.01); H01L 21/76846 (2013.01); H01L 21/76847 (2013.01); H01L 23/528 (2013.01); H01L 23/532 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 62/151 (2025.01); H10D 62/83 (2025.01); H10D 64/017 (2025.01); H10D 64/20 (2025.01); H10D 64/23 (2025.01); H10D 64/62 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 30/797 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a substrate comprising an active region;
a first epitaxial source/drain region extending into the active region;
a silicide layer over the first epitaxial source/drain region;
a first dielectric layer over the first epitaxial source/drain region;
a second dielectric layer over the first dielectric layer;
a first conductive feature in the second dielectric layer and extending through the first dielectric layer to the silicide layer;
a second conductive feature in the second dielectric layer and electrically coupled to the first conductive feature, wherein a bottom surface of the second conductive feature is a convex surface that is disposed in the second dielectric layer; and
a first barrier layer contacting a top surface of the first conductive feature and the bottom surface of the second conductive feature.