US 12,431,410 B2
Semiconductor device with polymer liner and method for fabricating the same
Shing-Yih Shih, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jan. 6, 2023, as Appl. No. 18/093,900.
Prior Publication US 2024/0234249 A1, Jul. 11, 2024
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76852 (2013.01); H01L 21/76898 (2013.01); H01L 23/53238 (2013.01); H01L 23/5329 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first substrate, having a front side and a back side opposite to the front side;
a first passivation layer over the front side of the first substrate;
a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate;
a conductive feature disposed in the first passivation layer, wherein the conductive feature comprises a conductive pad and an interconnect structure electrically connected to the conductive pad;
a through substrate via (TSV) penetrating through the second passivation layer and the first substrate, wherein the TSV is electrically coupled to the conductive feature;
a polymer liner between a sidewall of the TSV and the first substrate, wherein a top surface of the polymer liner is lower than the top surface of the second passivation layer; and
an isolation liner between the polymer liner and the first substrate.