US 12,431,403 B2
Semiconductor package including thermal interface material (TIM) layers on semiconductor chips
Kiwook Jung, Suwin-si (KR); Jaechoon Kim, Incheon (KR); Seunggeol Ryu, Seoul (KR); and Sungeun Jo, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-do (KP)
Filed on Mar. 8, 2022, as Appl. No. 17/689,707.
Claims priority of application No. 1020210114249 (KR), filed on Aug. 27, 2021.
Prior Publication US 2023/0060513 A1, Mar. 2, 2023
Int. Cl. H01L 23/34 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/34 (2013.01) [H01L 23/3107 (2013.01); H01L 23/5383 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate;
an interposer structure mounted on the package substrate;
a first semiconductor chip mounted on the interposer structure;
second semiconductor chips mounted on the interposer structure and adjacent to the first semiconductor chip;
an insulating filler disposed between the first and second semiconductor chips;
a first thermal interface material (TIM) layer arranged on the insulating filler;
second TIM layers arranged on the first and second semiconductor chips; and
a heat dissipation device contacting the first and second TIM layers,
wherein a thermal conductivity of each of the second TIM layers is higher than a thermal conductivity of the first TIM layer,
wherein the first TIM layer is disposed between the second TIM layers,
wherein the first TIM layer does not vertically overlap with either the first semiconductor chip or the second semiconductor chips,
wherein at least a portion of each of the second TIM layers vertically overlaps with the insulating filler,
wherein each of the second TIM layers comprises a liquid metal,
wherein one of the second TIM layers comprises:
a core layer; and
an oxide layer surrounding the core layer to cover an upper surface, a lower surface, and a side surface of the core layer, and
wherein the first TIM layer is disposed between the second TIM layers and includes a flat side surface facing one of the second TIM layers.