US 12,431,399 B2
Semiconductor device and method for manufacturing semiconductor device
Kazunori Fuji, Kyoto (JP); and Xiaopeng Wu, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Appl. No. 17/925,719
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed May 21, 2021, PCT No. PCT/JP2021/019392
§ 371(c)(1), (2) Date Nov. 16, 2022,
PCT Pub. No. WO2021/241447, PCT Pub. Date Dec. 2, 2021.
Claims priority of application No. 2020-091169 (JP), filed on May 26, 2020.
Prior Publication US 2023/0197544 A1, Jun. 22, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/29 (2006.01)
CPC H01L 23/293 (2013.01) [H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48151 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/186 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first insulating layer including a first obverse surface and a first reverse surface spaced apart from each other in a thickness direction, the first insulating layer being formed with a first penetrated part extending in the thickness direction;
a semiconductor element that includes an electrode corresponding to the first penetrated part and is in contact with the first obverse surface;
a first wiring layer including a first connecting part and a first main part, the first connecting part being arranged in the first penetrated part and in contact with the electrode, the first main part being connected to the first connecting part and disposed on the first reverse surface; and
a sealing resin in contact with the first obverse surface and covering the semiconductor element,
wherein the electrode has a connecting surface facing the first connecting part,
the connecting surface includes a first region that is exposed from the first insulating layer through the first penetrated part and a second region that is in contact with the first insulating layer, and
the first region has a greater surface roughness than the second region.