US 12,431,367 B2
Embedded package with shielding pad
Robert Fehler, Regensburg (DE); Angela Kessler, Sinzing (DE); Kushal Kshirsagar, Fremont, CA (US); Emanuele Bodano, Villach (AT); and Martin Benisek, Regensburg (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Mar. 17, 2023, as Appl. No. 18/122,895.
Prior Publication US 2024/0312799 A1, Sep. 19, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/538 (2006.01)
CPC H01L 21/565 (2013.01) [H01L 23/3121 (2013.01); H01L 23/3735 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 24/32 (2013.01); H01L 2224/32245 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1815 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a laminate package substrate comprising a first outer metallization layer at least partially at a first outer side of the laminate package substrate, and a first interior metallization layer that is below the first outer metallization layer;
first and second power transistor dies embedded within the laminate package substrate, the first and second power transistor dies each comprising a first load terminal and a second load terminal;
a driver die embedded within the laminate package substrate and comprising a plurality of I/O terminals facing the first outer side of the semiconductor package;
a plurality of I/O routings formed in the first interior metallization layer and electrically connected with the I/O terminals of the driver die;
a switching signal pad formed in the first outer metallization layer and electrically connected with the second load terminal of the first power transistor die and the first load terminal of the second power transistor die; and
a shielding pad formed in the first outer metallization layer that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies.