US 12,431,357 B2
Method for manufacturing high-voltage metal gate device
Xiaoliang Tang, Shanghai (CN); Haoyu Chen, Shanghai (CN); and Hua Shao, Shanghai (CN)
Assigned to Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed by Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed on Oct. 3, 2022, as Appl. No. 17/958,583.
Claims priority of application No. 202111320661.9 (CN), filed on Nov. 9, 2021.
Prior Publication US 2023/0142968 A1, May 11, 2023
Int. Cl. H01L 21/28 (2006.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01)
CPC H01L 21/28123 (2013.01) [H01L 21/28079 (2013.01); H10D 64/017 (2025.01); H10D 64/665 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A method for manufacturing a high-voltage metal gate device, wherein the method for manufacturing the high-voltage metal gate device comprises the following steps:
S1: after a pre-process, performing gate photolithography, etching, and sidewall processes to define at least one dummy poly gate, the at least one dummy poly gate is a dummy poly high-voltage gate, dummy polycrystalline of the dummy poly gate being formed on a gate dielectric layer;
S2: filling isolation dielectric between the dummy poly gates and performing a chemical-mechanical polishing (CMP) process;
S3: removing the dummy polycrystalline on the gate dielectric layer of the dummy poly gate through selective etching;
S4: depositing a gate metal on a wafer;
S5: performing a gate metal CMP process to reduce a thickness of the gate metal deposited on the wafer;
S6: depositing a blocking dielectric layer on the gate metal;
S7: opening a high-voltage gate region through photolithography, and removing blocking dielectric layer outside the high-voltage gate region through etching;
S8: performing a gate metal CMP process to reduce the thickness of the gate metal deposited on the wafer, wherein due to a blocking effect of the blocking dielectric layer, the gate metal in the high-voltage gate region is higher than the gate metal outside the high-voltage gate region; and
S9: removing the blocking dielectric layer on the gate metal in the high-voltage gate region through dry etching or acid pickling.