| CPC G11C 29/50004 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4087 (2013.01)] | 20 Claims |
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1. In a row decoder circuit controlling a plurality of word lines, the row decoder circuit comprising:
a power supply node;
a first node;
a first transistor connected to the power supply node and the first node;
a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a respective corresponding word line among the plurality of word lines;
a plurality of second transistors connected between the first node and the plurality of second nodes;
a plurality of third transistors connected between the plurality of second nodes and the power ground node; and
a comparator configured to output a detection signal based on a first voltage of the first node and a reference voltage,
wherein, in a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the plurality of third transistors are turned off, so that the first node and the plurality of second nodes are charged,
in a development period, the first transistor maintains a turned-on state, the plurality of second transistors are turned off, and each of the plurality of second nodes is discharged at a different rate depending on whether a current of a first respective corresponding word line is leaked,
in a sensing period, the first transistor is turned off, the plurality of second transistors are turned on, and the first node is selectively discharged according to a second voltage level of the plurality of second nodes connected in parallel, and
a first discharge rate of a defective word line among the plurality of word lines is faster than a second discharge rate of a non-defective word line among the plurality of word lines.
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