US 12,431,208 B2
Memory device detecting defect of word line path and operating method thereof
Taehong Kwon, Suwon-si (KR); and Daeseok Byeon, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 28, 2023, as Appl. No. 18/399,018.
Claims priority of application No. 10-2023-0011856 (KR), filed on Jan. 30, 2023.
Prior Publication US 2024/0296898 A1, Sep. 5, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/12005 (2013.01) [G11C 29/12015 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a memory block connected to a plurality of word lines;
a clock generator configured to generate a clock signal;
a charge pump circuit configured to generate a voltage to be provided to the plurality of word lines, based on the clock signal;
a row decoder configured to provide the voltage generated by the charge pump circuit to the memory block, wherein a word line path comprises an electrical connection from the charge pump circuit through a plurality of switches to the row decoder;
a current generation circuit connected from the word line path to a ground, the current generation circuit being configured to sink a current from the word line path for a reference time; and
a defect detection circuit configured to detect a defect on the word line path by comparing a first count value of the clock signal counted before the reference time with a second count value of the clock signal counted after the reference time,
wherein the first count value provides a reference value in a no-defect condition,
wherein the second count value is higher than the first count value based on the defect being a short circuit defect present in the word line path, and
wherein the second count value is lower than the first count value based on the defect being an open circuit defect present in the word line path.