| CPC G11C 16/3495 (2013.01) | 20 Claims |

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1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining whether a program erase cycle count associated with a segment of the memory device satisfies a first threshold criterion for triggering an offset bin update;
responsive to determining that the program erase cycle count satisfies the first threshold criterion, performing a calibration measurement of a center of a voltage valley for each state of each cell in the segment of the memory device;
repeating the calibration until a result of the calibration measurement is less than or equal to a threshold value; and
updating a threshold voltage offset bin associated with the segment of the memory device based on the result of the calibration measurement.
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