| CPC G11C 16/3459 (2013.01) [G11C 16/0433 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] | 18 Claims |
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1. A memory device, comprising:
a memory array comprising memory strings, a first word line, and a second word line, wherein each of the memory strings comprises a select gate transistor and memory cells, and wherein the first word line is coupled to a first memory cell of the memory cells, and the second word line is coupled to a second memory cell of the memory cells; and
a peripheral circuit coupled to the memory array and configured to, in a program/verify cycle:
apply, during a first time period, a program voltage to the first word line to program the first memory cell of the memory cells in a selected memory string of the memory strings;
apply, during a second time period after the first time period, a first verify voltage to the first word line to verify the first memory cell and a pass voltage to the second word line;
compare the first verify voltage with a target voltage so as to obtain a comparing result; and
in response to the comparing result indicative of the first verify voltage being higher than the target voltage, turn off, during a third time period between the first time period and the second time period, the select gate transistor in an unselected memory string of the memory strings,
wherein the target voltage is determined based, at least in part, on the pass voltage.
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