| CPC G11C 11/4074 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01); H02M 3/07 (2013.01)] | 20 Claims |
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1. A charge pump circuit for a semiconductor memory device, the charge pump circuit comprising:
a first pumping stage including:
a first pumping capacitor including a first end configured to receive a clock signal and a second end connected with a first node; and
a second pumping capacitor including a first end configured to receive an inverse clock signal and a second end connected with a second node;
a first transfer stage configured to transfer a voltage of the first node to a third node when the clock signal is at a high level or to transfer a voltage of the second node to a fourth node when the inverse clock signal is at the high level;
a second pumping stage including:
a third pumping capacitor including a first end connected with the third node and a second end connected with a fifth node; and
a fourth pumping capacitor including a first end connected with the fourth node and a second end connected with a sixth node; and
a second transfer stage configured to transfer a voltage of the fifth node to an output node when the clock signal is at the high level or to transfer a voltage of the sixth node to the output node when the inverse clock signal is at the high level,
wherein, when the clock signal is at the high level, the first pumping capacitor and the third pumping capacitor are electrically connected in series to the output node and output, to the output node, an output voltage that corresponds to multiple times an input voltage applied to the first pumping stage and the second pumping stage, and
wherein, when the inverse clock signal is at the high level, the second pumping capacitor and the fourth pumping capacitor are electrically connected in series to the output node and output, to the output node, the output voltage that corresponds to multiple times the input voltage.
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