| CPC G11C 11/40622 (2013.01) [G06F 12/0811 (2013.01); G06F 12/1433 (2013.01); G11C 11/40615 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01)] | 7 Claims |

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1. A memory system, comprising:
a normal memory area suitable for storing normal data;
a security memory area suitable for storing security data; and
a processor including a cache memory,
wherein the security memory area is allowed to be accessed, by the processor, only via the cache memory,
wherein the processor comprises a memory controller including a second row hammering detection circuit that counts activation numbers of rows of the security memory area in a full-row counting manner to detect rows to be refreshed.
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