| CPC G11C 11/40615 (2013.01) [G11C 11/40622 (2013.01); G11C 11/4078 (2013.01)] | 20 Claims |

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1. A memory device, comprising:
an array of memory cells having a plurality of wordlines, the array of memory cells arranged in a first dimensional direction and a second dimensional direction that is orthogonal to the first dimensional direction; and
counter circuitry disposed underneath the array of memory cells in a third dimensional direction that is orthogonal to the first dimensional direction and the second dimensional direction, the counter circuitry comprising a plurality of counters each corresponding to a respective one of the plurality of wordlines, where at least one of the plurality of counters is to be updated in response to each row activation.
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