US 12,431,181 B2
Memory device and memory system with table to determine refresh timing
Minseong Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Mar. 3, 2023, as Appl. No. 18/177,756.
Claims priority of application No. 10-2022-0129438 (KR), filed on Oct. 11, 2022.
Prior Publication US 2024/0119986 A1, Apr. 11, 2024
Int. Cl. G11C 11/406 (2006.01); G11C 11/4072 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/40618 (2013.01); G11C 11/4072 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of rows;
a time table including a plurality of fields respectively corresponding to the rows; and
a refresh control circuit configured to read field data from a k-th field of the time table according to an access command for a k-th row among the rows, where k is a natural number, determine whether to issue a refresh request signal for the k-th row based on current clock data and the field data, and update the field data of the k-th field using the current clock data so that each of the plurality of fields stores a last access time of a corresponding row,
wherein the refresh control circuit is configured to issue the refresh request signal whenever a difference between a decimal value of the updated field data for the last access time and a decimal value of the current clock data is greater than or equal to a preset refresh period, to thereby perform a refresh operation non-periodically according to an actual access point of each of the rows.