US 12,431,180 B2
Memory with programmable die refresh stagger
Dale H. Hiscock, Boise, ID (US); Michael Kaminski, Boise, ID (US); Joshua E. Alzheimer, Boise, ID (US); and John H. Gentry, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Oct. 7, 2022, as Appl. No. 17/962,188.
Application 17/962,188 is a continuation of application No. 17/234,725, filed on Apr. 19, 2021, granted, now 11,482,271.
Application 17/234,725 is a continuation of application No. 16/502,680, filed on Jul. 3, 2019, granted, now 10,991,413, issued on Apr. 27, 2021.
Prior Publication US 2023/0037145 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40611 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4096 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method by a memory system, comprising:
receiving a refresh command;
determining a first performance characteristic for refreshing a first memory apparatus based at least in part on the refresh command, wherein the first performance characteristic comprises a row refresh cycle time (tRFC) characteristic of the first memory apparatus that indicates a time allotted to the first memory apparatus to execute a refresh operation, and wherein determining the first performance characteristic includes analyzing the tRFC characteristic of the first memory apparatus; and
detecting, based at least in part on the first performance characteristic, a refresh group to which the first memory apparatus is assigned, wherein the refresh group is associated with a first time delay by which to delay executing one or more refresh operations at the first memory apparatus.