| CPC G11C 11/2257 (2013.01) [G11C 11/2275 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
a plurality of memory banks, each of the plurality of memory banks including:
a memory cell array including a plurality of memory cells connected with a plurality of word lines;
a row decoder connected with the memory cell array through the plurality of word lines;
a sense amplifier and write driver connected with the memory cell array through a plurality of bit lines;
a column decoder connected with the sense amplifier and write driver; and
control logic configured to receive a plurality of column address bits and a plurality of read commands,
wherein the control logic includes a processing-in-memory (PIM) address generator,
wherein, in a first operation mode, the control logic sends the plurality of column address bits to a memory bank of the plurality of memory banks, and
wherein, in a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.
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