US 12,431,173 B2
Memory package performing training operation using address-delay mapping and memory system including the same
Hwanseok Ku, Suwon-si (KR); Youngmin Jo, Suwon-si (KR); Anil Kavala, Suwon-si (KR); Jungjune Park, Suwon-si (KR); and Chiweon Yoon, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 25, 2023, as Appl. No. 18/494,258.
Claims priority of application No. 10-2023-0009871 (KR), filed on Jan. 26, 2023.
Prior Publication US 2024/0257848 A1, Aug. 1, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 8/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory package comprising:
a buffer device;
a data input/output pin connected to the buffer device and configured to receive a data signal;
a data strobe pin connected to the buffer device and configured to receive a data strobe signal; and
a plurality of memory devices connected to the buffer device and configured to operate based on the data signal and the data strobe signal,
wherein, in response to receiving the data strobe signal and training data in the data signal, the buffer device is configured to perform a training operation on the plurality of memory devices based on the training data and the data strobe signal, and
wherein, during the training operation, the buffer device is configured to set different delays on a plurality of sub-training data included in the training data, and the plurality of sub-training data are stored in different memory regions of the plurality of memory devices.