US 12,431,172 B2
Operation method for memory device
Shih-Chung Lee, Katsuradaiminami (JP); and Chi-Yuan Chin, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Feb. 14, 2023, as Appl. No. 18/168,638.
Prior Publication US 2024/0274169 A1, Aug. 15, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/08 (2006.01)
CPC G11C 7/1096 (2013.01) [G11C 7/22 (2013.01); G11C 8/08 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An operation method for a memory device, the operation method including:
selecting a selected word line from a plurality of word lines;
applying a program voltage to the selected word line; and
applying a pass voltage to a plurality of adjacent word lines adjacent to the selected word line,
wherein the pass voltage includes a first part and a second part,
a timing of the first part of the pass voltage is earlier than a timing of the second part of the pass voltage; and
a voltage of the first part of the pass voltage is higher than a voltage of the second part of the pass voltage,
wherein the voltage of the first part of the pass voltage is gradually increased until the pass voltage reaches a pass voltage maximum value, and the voltage of the second part of the pass voltage is gradually increased, wherein after a first predetermined pulse number or reaching a predetermined voltage, the voltage of the second part of the pass voltage is fixed.