US 12,431,171 B2
Page buffer, semiconductor device including page buffer, and operating method of semiconductor device
Won Jae Choi, Icheon-si (KR); and Duck Ju Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Sep. 26, 2023, as Appl. No. 18/475,028.
Claims priority of application No. 10-2023-0059630 (KR), filed on May 9, 2023.
Prior Publication US 2024/0379137 A1, Nov. 14, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); H03K 19/20 (2006.01)
CPC G11C 7/10 (2013.01) [G11C 7/12 (2013.01); G11C 8/08 (2013.01); H03K 19/20 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A page buffer comprising:
a bit line connection circuit configured to connect or disconnect a bit line and a first node;
a plurality of latch circuits, latch circuits being in parallel and connected to the first node; and
a logical operation circuit operatively coupled to the first node and configured to perform a logical operation on data that is represented by a voltage level on the first node using one or more of a voltage level of the first node and a voltage level of a second node, and configured to set the voltage level of the first node responsive to results of the logical operational operation.