| CPC G11C 5/063 (2013.01) [H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02)] | 20 Claims |
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1. A semiconductor memory device comprising:
a substrate comprising an element isolation layer;
a bit line that extends on the substrate in a first direction;
a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer;
a lower storage contact on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern;
a storage pad on the lower storage contact and connected to the lower storage contact; and
an information storage unit on the storage pad and connected to the storage pad,
wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other,
wherein a height from an upper surface of the lower storage contact to an upper surface of the storage pad is less than or equal to a height from the upper surface of the lower cell buffer insulating layer to the upper surface of the storage pad.
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