| CPC G09G 3/3233 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01)] | 14 Claims |

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1. A pixel driving circuit configured to drive a light-emitting element to emit light, the pixel driving circuit comprising:
a driving sub-circuit connected to the light-emitting element;
a data writing sub-circuit electrically connected to a data signal terminal, a scanning signal terminal and the driving sub-circuit, and configured to write a data signal from the data signal terminal into the driving sub-circuit and apply the data signal from the data signal terminal to a leakage current compensation point, under control of a scanning signal from the scanning signal terminal; and
a light-emitting control sub-circuit electrically connected to the driving sub-pixel, a light-emitting control signal terminal and the light-emitting element, and configured to control the driving sub-circuit to output a driving current related to the data signal to the light-emitting element under control of a light-emitting control signal from the light-emitting control signal terminal, wherein a voltage of a control electrode of the driving sub-circuit is compensated by a voltage of the leakage current compensation point in a process of emitting light by the light-emitting element,
wherein the data writing sub-circuit comprises a first transistor (T8), a second transistor (T4) and a first dual gate transistor (T1-1 T1-2), the scanning signal terminal comprises a first scanning signal terminal (SK) and a third scanning signal terminal (SS), and the leakage current compensation point comprises a first leakage current compensation point (A),
wherein a control electrode of the first transistor (T8) is electrically connected to the first scanning signal terminal (SK), a first electrode of the first transistor (T8) is electrically connected to a second electrode of the second transistor (T4), and a second electrode of the first transistor (T8) is electrically connected to an input terminal of the driving sub-circuit, and
wherein a control electrode of the second transistor (T4) is electrically connected to the third scanning signal terminal (SS), a first electrode of the second transistor (T4) is electrically connected to the data signal terminal (Vdata), and the second electrode of the second transistor (T4) is electrically connected to the first leakage current compensation point (A) between dual gates of the first dual gate transistor.
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