US 12,431,081 B2
Display device
Jang Mi Kang, Seoul (KR); Ji Sun Kim, Seoul (KR); and Mu Kyung Jeon, Ulsan (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Sep. 13, 2023, as Appl. No. 18/367,981.
Application 18/367,981 is a continuation of application No. 17/888,487, filed on Aug. 16, 2022, granted, now 11,783,783.
Application 17/888,487 is a continuation of application No. 17/135,806, filed on Dec. 28, 2020, granted, now 11,462,178, issued on Oct. 4, 2022.
Application 17/135,806 is a continuation of application No. 16/129,796, filed on Sep. 13, 2018, granted, now 10,878,759, issued on Dec. 29, 2020.
Claims priority of application No. 10-2017-0118887 (KR), filed on Sep. 15, 2017.
Prior Publication US 2024/0005878 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/20 (2006.01); G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); G09G 3/3266 (2016.01); G09G 3/3283 (2016.01); G09G 3/3291 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 3/3283 (2013.01); G09G 3/3291 (2013.01); H10D 86/421 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/471 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/043 (2013.01); G09G 2310/0264 (2013.01); H10K 59/12 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A display device comprising:
a light-emitting diode;
a first transistor electrically connected to the light-emitting diode to supply a driving current to the light-emitting diode, the first transistor comprising a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first electrode, and a second electrode which is electrically connected to the light-emitting diode;
a first scan line configured to transmit a first signal to a second gate electrode of a second transistor, the second gate electrode being a portion of the first scan line;
a second scan line configured to transmit a second signal to a third gate electrode of a third transistor, the third gate electrode being a portion of the second scan line; and
a conductive pattern physically connected to the first gate electrode,
wherein:
the conductive pattern overlaps the first scan line and the second scan line in the plan view; and
one of the second transistor and the third transistor is a PMOS transistor, and the other one of the second transistor and the third transistor is an NMOS transistor.