| CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); H10K 59/131 (2023.02); G09G 2310/061 (2013.01); G09G 2320/0204 (2013.01)] | 18 Claims |

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1. A display substrate, comprising:
a base substrate;
a plurality of sub-pixels arranged in an array on the base substrate, each of the sub-pixels comprising a light-emitting drive circuit, a reset circuit, a compensation circuit, a light-emitting control circuit and a light-emitting element; wherein the light-emitting drive circuit and the reset circuit are connected to the light-emitting element, the light-emitting drive circuit is configured to provide a drive signal to the light-emitting element, and the reset circuit is configured to provide a reset signal to the light-emitting element; the compensation circuit is connected to the light-emitting drive circuit, and the compensation circuit is configured to provide a compensation signal to the light-emitting drive circuit; the light-emitting control circuit is connected to the light-emitting drive circuit, and configured to provide a DC power supply signal to the light-emitting drive circuit;
wherein at least two of the sub-pixels share a same target circuit, and the target circuit comprises the reset circuit, the compensation circuit and the light-emitting control circuit;
the light-emitting control circuit in each of the sub-pixels comprises a light-emitting transistor, a gate of the light-emitting transistor is connected to a light-emitting control signal line, a first electrode of the light-emitting transistor is connected to a DC power supply terminal, and a second electrode of the light-emitting transistor is connected to the light-emitting drive circuits of the at least two of the sub-pixels which share the light-emitting control circuit, the light-emitting control circuit is configured to provide a DC power supply signal from the DC power supply terminal to the light-emitting drive circuits of the at least two of the sub-pixels in response to a light-emitting control signal from the light-emitting control signal line;
the light-emitting drive circuit in each of the sub-pixels comprises a data write sub-circuit, the data write sub-circuit is connected to one of a plurality of first gate lines, one of a plurality of data lines and a first node, and the data write sub-circuit is configured to provide a data signal from the data line to the first node in response to a first gate drive signal from the first gate line;
the reset circuit is connected to one of a plurality of second gate lines, a reset signal terminal and a second node, and the reset circuit is configured to provide a reset signal from the reset signal terminal to the second node in response to the second gate drive signal from the second gate line; and
the compensation circuit is connected to one of a plurality of third gate lines, a compensation signal terminal and the first node, and the compensation circuit is configured to provide a compensation signal from the compensation signal terminal to the first node in response to a third gate drive signal from the third gate line.
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