| CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |

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1. A gate driving circuit comprising:
a first pull up control circuit configured to control a voltage of a pull up control node in response to a previous carry signal which is one of carry signals of previous stages;
a pull down control circuit configured to control a voltage of a pull down control node in response to the voltage of the pull up control node;
a boosting circuit including a boosting capacitor and configured to boost the voltage of the pull up control node;
a gate output circuit configured to output a plurality of gate signals having different timings in response to the voltage of the pull up control node and the voltage of the pull down control node; and
a stabilizing circuit including a control electrode connected to a first end of the boosting capacitor, a first electrode configured to receive a first high power voltage and a second electrode connected to the first pull up control circuit,
wherein the pull up control node is connected to a second end of the boosting capacitor opposite to the first end.
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