| CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] | 18 Claims |

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1. A display panel, comprising:
a substrate having a display region and a peripheral region at least partially surrounding the display region;
a plurality of pixels arranged in an array and disposed in the display region;
a first drive circuit disposed in the peripheral region, the first drive circuit comprising: a plurality of first drive units cascaded, and a plurality of first gating units in one-to-one correspondence with the plurality of first drive units;
a second drive circuit disposed in the peripheral region, the second drive circuit comprising:
a plurality of second drive units cascaded, and a plurality of second gating units in one-to-one correspondence with the plurality of second drive units,
wherein at least one of the first drive units and at least one of the second drive unit are respectively disposed on both sides of the substrate in a pixel row direction, each of the first gating units and a corresponding first drive unit are disposed on a same side of the substrate, and each of the second gating units and a corresponding second drive unit are disposed on a same side of the substrate; among the plurality of first drive units, one part of the first drive units are disposed on a first side of the both sides, and a rest of the first drive units other than the one part of the first drive units are disposed on a second side of the both sides; and among the plurality of second drive units, one part of the second drive units are disposed on the first side of the both sides, and a rest of the second drive units other than the one part of the second drive units are disposed on the second side of the both sides;
each of the first drive units is coupled with one part of pixels in at least one row of pixels by a corresponding first gating unit, which is also coupled with a first enable line and is configured to control on-off between the first drive unit and the one part of the pixels based on a first enable signal provided by the first enable line; and the plurality of first drive units are also coupled with a first turn-on line and are configured to output first gate driving signals based on a first turn-on signal provided by the first turn-on line; and
each of the second drive units is coupled with another part of the pixels in the at least one row of pixels by a corresponding second gating unit, which is also coupled with a second enable line and is configured to control on-off between the second drive unit and the another part of the pixels based on a second enable signal provided by the second enable line; and the plurality of second drive units are also coupled with a second turn-on line and are configured to output second gate driving signals based on a second turn-on signal provided by the second turn-on line.
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