US 12,430,804 B2
Memory allocation technologies for data compression and de-compression
Prasoonkumar Surti, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Karol A. Szerszen, Hillsboro, OR (US); Karthik Vaidyanathan, San Francisco, CA (US); Sreenivas Kothandaraman, Sammamish, WA (US); and Mohamed Farook, Tamilnadu (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 18, 2021, as Appl. No. 17/405,957.
Prior Publication US 2023/0062540 A1, Mar. 2, 2023
Int. Cl. G06T 9/00 (2006.01); H03M 7/30 (2006.01)
CPC G06T 9/00 (2013.01) [H03M 7/3064 (2013.01); H03M 7/3066 (2013.01); H03M 7/6011 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
at least one memory device and
compression circuitry to compress a region of pixel data by representation of at least one channel of the region of pixel data with respect to a seed value, wherein
the representation is associated with one of at least two partitions,
the compression circuitry is to determine a number of bits used to encode the representation based on an associated partition,
to determine the number of bits used to encode the representation based on the associated partition, the compression circuitry is to determine a bin boundary between two partitions of the at least two partitions based on a range of bins,
the determine the number of bits used to encode the representation based on the associated partition is based on a fewest number of bits to encode a distribution of representations in the at least two partitions, and
the compression circuitry is to encode the representation based on the determined number of bits.