US 12,430,488 B2
Methods of designing layout of semiconductor device and methods for manufacturing semiconductor device using the same
Sungwe Cho, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 17, 2024, as Appl. No. 18/638,199.
Application 18/638,199 is a division of application No. 17/517,126, filed on Nov. 2, 2021, granted, now 11,989,497.
Claims priority of application No. 10-2021-0008813 (KR), filed on Jan. 21, 2021.
Prior Publication US 2024/0265184 A1, Aug. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); G06F 30/398 (2020.01); H10D 89/10 (2025.01); G06F 111/04 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/398 (2020.01); H10D 89/10 (2025.01); G06F 2111/04 (2020.01)] 6 Claims
OG exemplary drawing
 
1. A method of designing a layout of a semiconductor device, comprising:
preparing a standard cell library comprising information on standard cells;
determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library, wherein the common pattern region comprises a common active pattern;
adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and
arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells or to overlap the common pattern region based on a width of the common active pattern.