US 12,430,265 B2
Hybrid microprocessor and programmable logic device (PLD)-based architecture including inter processor communication
Rajesh Madathikandam, Karnataka (IN); Robin David Hill, Solihull (GB); Stephen Potter, Nuneaton (GB); Ashish Vijay, Rajasthan (IN); Rajeeva Krishna, Bangalore (IN); and Anitha Thangavel, Karnataka (IN)
Assigned to HAMILTON SUNDSTRAND CORPORATION, Charlotte, NC (US)
Filed by Hamilton Sundstrand Corporation, Charlotte, NC (US)
Filed on Sep. 27, 2023, as Appl. No. 18/475,829.
Claims priority of application No. 202311029885 (IN), filed on Apr. 25, 2023.
Prior Publication US 2024/0362173 A1, Oct. 31, 2024
Int. Cl. G06F 13/12 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/124 (2013.01) [G06F 11/1004 (2013.01); G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microprocessor-PLD hybrid architecture comprising:
an inter-processor communication (IPC) microprocessor configured to output a data read command configured to initiate a data read operation that obtains first data or to output a data write command configured to initiate a data write operation that stores second data; and
a programmable logic device (PLD) in signal communication with the IPC microprocessor via an IPC interface, the PLD comprising:
a plurality of PLD modules, each of the PLD modules including PLD memory configured to store data; and
a bus controller in signal communication with the plurality of PLD modules via a plurality of PLD interfaces, the bus controller including a bus memory unit configured to store data and including a bus controller engine configured to sequentially execute a set of bus controller instructions,
wherein the bus controller reads the first data from a target PLD module from among the plurality of PLD modules in response to receiving the data read command, and transfers the first data to the IPC microprocessor, and
wherein the bus controller receives the second data from the IPC microprocessor, and stores the second data in a target PLD module from among the plurality of PLD modules in response to receiving the data write command.