US 12,430,263 B2
Translation lookaside buffer to implement adapative page size
Zhaojuan Bian, Shanghai (CN); and Kebing Wang, Shanghai (CN)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 21, 2023, as Appl. No. 18/187,092.
Application 18/187,092 is a continuation of application No. 16/973,998, granted, now 11,615,034, previously published as PCT/CN2018/108215, filed on Sep. 28, 2018.
Prior Publication US 2023/0281134 A1, Sep. 7, 2023
Int. Cl. G06F 12/10 (2016.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0871 (2016.01); G06F 12/0882 (2016.01); G06F 12/1045 (2016.01)
CPC G06F 12/1045 (2013.01) [G06F 12/0246 (2013.01); G06F 12/0653 (2013.01); G06F 12/0871 (2013.01); G06F 12/0882 (2013.01); G06F 2212/7201 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a processor of a computing device, a request to access a physical memory communicatively coupled to the processor, the request comprising a virtual page number and identifying data; and
translating the virtual page number to a physical address in the physical memory based on the identifying data from the request, wherein the physical memory includes one or more indicator fields having an extensible size indicator field or an actual size indicator field, wherein the extensible size indicator field represents an amount of the physical memory reserved for a page in the physical memory.