US 12,430,262 B2
Processing device and method of updating translation lookaside buffer thereof
Chang-Hyo Yu, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Jun. 4, 2024, as Appl. No. 18/733,709.
Application 18/733,709 is a continuation of application No. 18/500,781, filed on Nov. 2, 2023, granted, now 12,038,850.
Claims priority of application No. 10-2022-0186294 (KR), filed on Dec. 27, 2022.
Prior Publication US 2024/0378157 A1, Nov. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1027 (2016.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01)
CPC G06F 12/1027 (2013.01) [G06N 3/04 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing device configured to cause:
generating a task for a machine learning operation of a machine learning model to be assigned to processing circuitry;
determining, based on at least one of a characteristic of the task or a type of a memory accessed by the task, whether a translation table is updated in a push mode for a translation memory of the processing circuitry, wherein the translation table specifies relationship between virtual memory addresses and physical memory addresses;
in response to a determination that the translation table is updated in the push mode, pushing an update signal comprising update information to the translation table into the translation memory of the processing circuitry and updating the translation table using the update information; and
in response to a determination that the translation table is not updated in the push mode, assigning the task to the processing circuitry without pushing the update signal comprising the update information to the translation table into the translation memory of the processing circuitry,
wherein the processing circuitry is configured to process the task based on the translation table in the translation memory to generate an output,
the processing device processes the machine learning operation of the machine learning model based on the output from the processing circuitry.