US 12,430,241 B2
Memory controller, memory controller control method, and memory system
Katsuyuki Shimada, Tokyo (JP); and Yuki Komatsu, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2023, as Appl. No. 18/460,516.
Claims priority of application No. 2022-148516 (JP), filed on Sep. 16, 2022.
Prior Publication US 2024/0095162 A1, Mar. 21, 2024
Int. Cl. G06F 12/02 (2006.01); G06N 3/0455 (2023.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01)
CPC G06F 12/0246 (2013.01) [G06N 3/0455 (2023.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a compression unit configured to compress n determination voltage values for threshold voltages of a memory cell to a vector quantity including a total of m vector components, where n and m are integers satisfying the relationship n>m≥2, the memory cell being capable of storing three or more data values therein according to the n determination voltage values;
a storing unit configured to store the vector quantity into a memory region; and
a decompression unit configured to decompress the stored vector quantity to provide the n determination voltage values for reading data values from or writing data values to the memory cell.