US 12,430,224 B2
Debug trace of cache memory requests
Andrew J. Beaumont-Smith, Cambridge, MA (US); Sandeep Gupta, San Mateo, CA (US); Krishna C. Potnuru, San Jose, CA (US); and Matthias Knoth, Scotts Valley, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 29, 2023, as Appl. No. 18/344,170.
Application 18/344,170 is a continuation of application No. 17/538,939, filed on Nov. 30, 2021, granted, now 11,740,993.
Claims priority of provisional application 63/239,349, filed on Aug. 31, 2021.
Prior Publication US 2023/0418724 A1, Dec. 28, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 12/02 (2006.01)
CPC G06F 11/348 (2013.01) [G06F 11/3037 (2013.01); G06F 12/0223 (2013.01); G06F 2212/1008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of processor circuits;
a cache memory circuit; and
a trace control circuit configured to, in response to activation of a particular debug mode:
monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit;
determine that a particular one of the monitored memory requests is a read request that results in a cache miss;
in response to the determination, store, in allocated space in a trace buffer, information associated with the particular monitored memory request; and
in response to a determination that available capacity in the trace buffer fails to satisfy a threshold level, assert a respective stall request signal to one or more of the processor circuits, wherein a given stall request signal causes the one or more processor circuits to cease further processing of instructions until the respective stall request signal is de-asserted.