US 12,430,205 B2
Methods for error count reporting with scaled error count information, and memory devices employing the same
Matthew A. Prather, Boise, ID (US); and Randall J. Rooney, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on May 1, 2024, as Appl. No. 18/652,714.
Application 18/652,714 is a continuation of application No. 18/200,439, filed on May 22, 2023, granted, now 11,977,444.
Application 18/200,439 is a continuation of application No. 17/372,453, filed on Jul. 10, 2021, granted, now 11,698,831, issued on Jul. 11, 2023.
Application 17/372,453 is a continuation of application No. 16/509,417, filed on Jul. 11, 2019, granted, now 11,074,126, issued on Jul. 27, 2021.
Claims priority of provisional application 62/697,293, filed on Jul. 12, 2018.
Prior Publication US 2024/0289219 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G11C 13/00 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G06F 2201/88 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method by a memory system, comprising:
performing an error control operation at one or more memory arrays of the memory system;
identifying a quantity of errors associated with the one or more memory arrays based at least in part on performing the error control operation;
comparing the quantity of errors to one or more threshold values; and
storing, in a register associated with the one or more memory arrays, an indication that the quantity of errors satisfies the one or more threshold values.