US 12,430,140 B2
Per-lane power management of bus interconnects
Travis T. Schluessler, Berthoud, CO (US); Huimin Chen, Beaverton, OR (US); Selvakumar Panneer, Portland, OR (US); and Zhengmin Li, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 7, 2021, as Appl. No. 17/468,179.
Prior Publication US 2023/0076468 A1, Mar. 9, 2023
Int. Cl. G06F 9/445 (2018.01); G06F 9/4401 (2018.01); G06F 13/20 (2006.01)
CPC G06F 9/44505 (2013.01) [G06F 9/4418 (2013.01); G06F 13/20 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a request for a transfer of data on a communication bus of a computing device;
determining a direction for the transfer, at least in part based on the request;
determining a quantity of data for the transfer, at least in part based on the request;
determining a power state for a lane of the communication bus, the lane to be used for the transfer, the power state determination being at least in part based on the direction and the quantity of data for the transfer;
setting the power state for the lane of the communication bus; and
scheduling a wake or sleep initiation time for the lane of the communication bus.