US 12,430,108 B2
Multistage compiler architecture
Ulf Hanebutte, Gig Harbor, WA (US); Senad Durakovic, Palo Alto, CA (US); Chien-Chun Chou, Morgan Hill, CA (US); Fu-Hwa Wang, Saratoga, CA (US); and Mohana Tandyala, Fremont, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Mar. 2, 2022, as Appl. No. 17/684,871.
Application 17/684,871 is a continuation in part of application No. 17/390,143, filed on Jul. 30, 2021, granted, now 11,467,811.
Claims priority of provisional application 63/230,598, filed on Aug. 6, 2021.
Claims priority of provisional application 63/214,651, filed on Jun. 24, 2021.
Prior Publication US 2023/0004365 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/44 (2018.01); G06F 8/41 (2018.01)
CPC G06F 8/44 (2013.01) [G06F 8/425 (2013.01)] 40 Claims
OG exemplary drawing
 
1. A system, comprising:
a computing device including a processor;
a compiler running on the computing device, wherein the compiler includes a plurality of compiler blocks, wherein compiler blocks of the plurality of compiler blocks are compossible, and wherein the compiler is configured to
identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code associated with an application;
determine one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware; and
compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware,
wherein the compiler comprises a frontend compiler and a backend compiler, and wherein the backend compiler comprises the plurality of compiler blocks, and wherein the plurality of compiler blocks is configured to generate a plurality of structured metadata that includes information associated with the the one or more resources in the hardware and the one or more processing operations, and wherein a structured metadata from the plurality of structured metadata is selected and fed back into one compiler block of the plurality of compiler blocks of the backend compiler, and wherein the selected structured metadata is used by the one compiler block of the plurality of compiler blocks of the backend compiler.