| CPC G06F 7/5443 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01)] | 21 Claims |
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1. A Gain Balanced Analog Multiplier Accumulator (AMAC) comprising:
a differential charge transfer bus;
an inference memory storing a plurality of X input values and W coefficient values;
a Multiply-Accumulate (MAC) controller coupled to the inference memory to output a subset of the X input values and associated W coefficient values;
a plurality of MAC unit elements (MAC UEs) performing multiply-accumulate operations on the X input and the W input of the subset of the X input values and associated W coefficient values during conversion cycles, each MAC UE having an X input and a W input with individual bits coupled to respective logic gates, each logic gate performing a bitwise multiplication as a logic gate output, each logic gate output coupled through a respective binary-weighted capacitor to the differential charge transfer bus, thereby transferring a binary weighted charge to the differential charge transfer bus corresponding to a weighted multiplication result on each conversion cycle, each MAC UE having an associated gain error;
the MAC controller addressing the inference memory to arrange the subset of the X input values and associated W coefficient values to a different MAC UE of the plurality of MAC UEs for subsequent multiplication operations, thereby reducing a gain error contributed by a particular MAC UE;
and wherein each logic gate is a NAND gate having an X binary input and a W binary input, and each bit of the X binary input and each bit of the W binary input are applied to a respective NAND gate, the respective NAND gate having an output and a complement output, each output and complement output coupled to the differential charge transfer bus through capacitors with relative weights of 1, 2, 4, 2, 4, 8, 4, 8, and 16.
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