| CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 16 Claims |
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1. A method for reading data from a memory device, comprising:
providing on a first chip:
a serial peripheral interface (SPI) memory controller;
providing on a second chip:
a memory device that includes flash memory control circuitry that includes read control circuitry and a cache, and a flash memory array coupled to the flash memory control circuitry;
receiving, by the SPI memory controller coupled to the memory device, a host system read request;
determining, by the SPI controller, whether the host system read request indicates beginning at a next address continuing from a last address associated with a preceding host system read request;
providing, by the SPI controller, the memory device read command to the memory device, wherein the memory device read command is the first type when the host system read request does not indicate beginning at the next address continuing from the last address, and wherein the memory device read command is the second type when the host system read request indicates beginning at the next address continuing from the last address;
receiving the memory device read command with the read control circuitry;
determining with the read control circuitry whether the received memory device read command is a first type or a second type;
providing data from the memory device in response to the received memory device read command, including reading the data from the flash memory array beginning at an address associated with the received memory device read command when the received memory device read command is the first type, and including reading the data from the cache when the received memory device read command is the second type;
reading data with the read control circuitry from the flash memory array into the cache in response to the received memory device read command; and
storing in a register that is part of the read control circuitry, a last address read from the flash memory array after reading all data responsive to the received memory device read command, the read control circuitry reads data from the flash memory array into the cache starting at the last address stored in the register when the received memory device read command is the second type.
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