US 12,430,064 B2
Memory controller, operation method thereof, and memory system
Soonyoung Kang, Suwon-si (KR); and Dongmin Shin, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 7, 2024, as Appl. No. 18/737,403.
Claims priority of application No. 10-2023-0079935 (KR), filed on Jun. 21, 2023; and application No. 10-2023-0124276 (KR), filed on Sep. 18, 2023.
Prior Publication US 2024/0427520 A1, Dec. 26, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device configured to
read hard decision data from a memory cell array based on a hard read voltage,
read first soft decision data from the memory cell array based on two or more first soft read voltages, the two or more first soft read voltages obtained based on the hard read voltage and a first voltage offset,
generate a first compressed sub-segment based on encoding a position of a bit having a first value into a position value for each first soft decision sub-segment of a plurality of first soft decision sub-segments in the first soft decision data, and
output first compressed data including a plurality of first compressed sub-segments; and
a memory controller configured to
receive the first compressed data,
count the number of position values in each first compressed sub-segment of the plurality of first compressed sub-segments, and
provide, to the memory device, a command based on the counted number, the command requesting a change of a voltage offset and a recompression operation.