US 12,430,032 B2
Apparatus and method for handling memory access requests
Jamshed Jalal, Austin, TX (US); Gurunath Ramagiri, Austin, TX (US); Tushar P Ringe, Austin, TX (US); Mark David Werkheiser, Austin, TX (US); Ashok Kumar Tummala, Austin, TX (US); and Dimitrios Kaseridis, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 18/000,761
Filed by Arm Limited, Cambridge (GB)
PCT Filed May 20, 2021, PCT No. PCT/GB2021/051223
§ 371(c)(1), (2) Date Dec. 5, 2022,
PCT Pub. No. WO2021/250371, PCT Pub. Date Dec. 16, 2021.
Claims priority of application No. 20386030 (EP), filed on Jun. 10, 2020.
Prior Publication US 2023/0221866 A1, Jul. 13, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 12 Claims
OG exemplary drawing
 
12. A method of handling memory access requests comprising:
providing an interconnect to couple a plurality of requester elements with a plurality of slave elements, the plurality of requester elements being arranged to issue the memory access requests for processing by the plurality of slave elements;
employing an intermediate element provided within the interconnect to act as a point of serialisation to order the memory access requests issued by the plurality of requester elements via the intermediate element;
tracking, within tracking circuitry of the intermediate element shared between the plurality of slave elements and having a plurality of entries, handling of the memory access requests accepted by the intermediate element;
mapping, within address mapping circuitry of the intermediate element, specified address ranges to a target identifier used to indicate a target slave element to be used for access to that address range and to information indicative of bandwidth capability for the target slave element; and
in response to receipt by the intermediate element of a given memory access request, identifying the target slave element amongst the plurality of slave elements for that given memory access request using the address mapping circuitry, and determining whether the given memory access request is to be accepted by the intermediate element acting as the point of serialization, by determining whether there is a free entry in the interconnect usable for the given memory access request without causing an entry threshold to be exceeded, the entry threshold being dependent on the information indicative of bandwidth capability for the target slave element provided by the address mapping circuitry.