US 12,430,024 B2
Multiple tier storage deployment management engine
Sanjeev Trika, Portland, OR (US); Kapil Karkra, Chandler, AZ (US); and Mariusz Barczak, Gdansk (PL)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,755.
Prior Publication US 2022/0107733 A1, Apr. 7, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 11/30 (2006.01)
CPC G06F 3/0607 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0638 (2013.01); G06F 3/0685 (2013.01); G06F 11/3034 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An electronic apparatus, comprising:
a processor;
memory communicatively coupled to the processor; and
circuitry communicatively coupled to the processor and the memory to:
determine a group of available types of persistent memory devices and a set of characteristics associated with each type of persistent memory device of the group of available types of persistent memory devices,
determine of a set of requirements for a storage system,
determine a deployment configuration for the storage system with a lowest storage acquisition cost based on the group of available types of persistent memory devices, the sets of characteristics, and the set of requirements,
determine one or more deployed persistent memory devices at runtime,
collect runtime information for the one or more deployed persistent memory devices,
determine one or more types of available persistent memory devices for the group of available types of persistent memory devices based on the one or more deployed persistent memory devices, and
determine one or more sets of characteristics respectively associated with the determined one or more types based on the collected runtime information for the one or more deployed persistent memory devices.