US 12,429,904 B2
Heterogeneous computing systems and methods for clock synchronization
Jay Sterling Coggin, Brooklyn, NY (US); Marc Carino, Venice, CA (US); Fabian Renn-Giles, West Drayton (GB); Mark Rakes, Venice, CA (US); and Afrooz Family, Los Angeles, CA (US)
Assigned to SYNG, Inc., Marina del Rey, CA (US)
Filed by SYNG, Inc., Marina del Rey, CA (US)
Filed on Nov. 28, 2023, as Appl. No. 18/522,071.
Application 18/522,071 is a continuation of application No. 17/457,637, filed on Dec. 3, 2021, granted, now 11,868,175.
Claims priority of provisional application 63/121,147, filed on Dec. 3, 2020.
Prior Publication US 2024/0353889 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/12 (2006.01)
CPC G06F 1/12 (2013.01) 20 Claims
OG exemplary drawing
 
1. A heterogeneous clock synchronization system, comprising:
a reference device comprising:
a clock circuitry; and
a transmitter;
where the transmitter is configured to transmit a synchronization signal based on a clock signal generated by the clock circuitry; and
at least one receiving device comprising:
a processor, directed by a general-purpose operating system (GPOS);
a coprocessor, directed by a real-time operating system (RTOS);
a memory accessible by the processor and the coprocessor; and
a receiver;
where the RTOS directs the coprocessor to:
trigger an interrupt upon reception, by the receiving device using the receiver, of the synchronization signal;
sample a GPOS clock time stored in the memory in response to the interrupt;
generate a synchronized clock time based on the synchronization signal and the sampled GPOS clock time, where the synchronized clock time is synchronized to the clock signal of the reference device; and
store the synchronized clock time in the memory.