US 12,429,521 B2
JTAG standard pin test system
Qiu-Yue Duan, Shanghai (CN); Xin-Ying Xie, Shanghai (CN); and Lin Zhang, Shanghai (CN)
Assigned to SQ Technology (Shanghai) Corporation, Shanghai (CN); and Inventec Corporation, Taipei (TW)
Filed by SQ Technology (Shanghai) Corporation, Shanghai (CN); and Inventec Corporation, Taipei (TW)
Filed on Feb. 29, 2024, as Appl. No. 18/592,227.
Claims priority of application No. 202311675216.3 (CN), filed on Dec. 7, 2023.
Prior Publication US 2025/0189581 A1, Jun. 12, 2025
Int. Cl. G01R 31/3185 (2006.01)
CPC G01R 31/318572 (2013.01) 9 Claims
OG exemplary drawing
 
1. A boundary-scan standard pin test system, comprising:
a to-be-tested board, having to-be-tested slots, wherein the to-be-tested slots are electrically connected to form different to-be-tested series chains;
riser cards, wherein each of the riser cards has a riser card insertion interface, a riser-card edge-connector interface, a first boundary-scan input interface, a first boundary-scan output interface, a second boundary-scan input interface, and a second boundary-scan output interface, wherein test data input (TDI) pins of the riser card insertion interface, the riser-card edge-connector interface, the first boundary-scan input interface, the first boundary-scan output interface, the second boundary-scan input interface, and the second boundary-scan output interface are electrically connected to each other, test data output (TDO) pins of the riser card insertion interface, the riser-card edge-connector interface, the first boundary-scan input interface, the first boundary-scan output interface, the second boundary-scan input interface, and the second boundary-scan output interface are electrically connected to each other, test clock (TCK) pins of the riser card insertion interface, the riser-card edge-connector interface, the first boundary-scan input interface, the first boundary-scan output interface, the second boundary-scan input interface, and the second boundary-scan output interface are electrically connected to each other, test mode select (TMS) pins of the riser card insertion interface, the riser-card edge-connector interface, the first boundary-scan input interface, the first boundary-scan output interface, the second boundary-scan input interface, and the second boundary-scan output interface are electrically connected to each other, and test reset (TRST) pins of the riser card insertion interface, the riser-card edge-connector interface, the first boundary-scan input interface, the first boundary-scan output interface, the second boundary-scan input interface, and the second boundary-scan output interface are electrically connected to each other,
wherein the riser-card edge-connector interface of each of the riser cards is inserted into a corresponding one of the to-be-tested slots, so that the inserted riser-card edge-connector interface is electrically connected to TDI pins, the TDO pins, the TCK pins, the TMS pins, and the TRST pins of the corresponding one of the to-be-tested slots;
test cards, wherein each of the test cards has a boundary scan component, a boundary-scan input interface, a boundary-scan output interface, and an edge connector interface, wherein TDI pins of the boundary scan component, the boundary-scan input interface, the boundary-scan output interface, and the edge connector interface are electrically connected to each other, TDO pins of the boundary scan component, the boundary-scan input interface, the boundary-scan output interface, and the edge connector interface are electrically connected to each other, TCK pins of the boundary scan component, the boundary-scan input interface, the boundary-scan output interface, and the edge connector interface are electrically connected to each other, TMS pins of the boundary scan component, the boundary-scan input interface, the boundary-scan output interface, and the edge connector interface are electrically connected to each other, and TRST pins of the boundary scan component, the boundary-scan input interface, the boundary-scan output interface, and the edge connector interface are electrically connected to each other,
wherein, the edge connector interface of each of the test cards is inserted into the riser card insertion interface of a corresponding one of the riser cards, so that the inserted edge connector interface is electrically connected to the TDI pins, the TDO pins, the TCK pins, the TMS pins, and the TRST pins of the riser card insertion interface of the corresponding one of the riser cards,
wherein each of the test cards performs a boundary-scan standard pin test on a boundary-scan format test signal provided from the corresponding one of the to-be-tested slots and outputs a boundary-scan format test result signal;
a test access port (TAP) controller, electrically connected to different to-be-tested series chains, and configured to convert test data into corresponding boundary-scan format test signals and provide the boundary-scan format test signals to the different to-be-tested series chains, respectively, receives the boundary-scan format test result signals from the to-be-tested series chains, and converts the received boundary-scan format test result signals into response data; and
a test data generating device, electrically connected to the TAP controller, and configured to provide the test data to the TAP controller, and receive the response data corresponding to the to-be-tested slots from the TAP controller.