US 12,101,065 B2
Dual voltage switched branch LNA architecture
Miles Sanner, San Diego, CA (US); Emre Ayranci, Costa Mesa, CA (US); and Parvez Daruwalla, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Oct. 23, 2023, as Appl. No. 18/492,544.
Application 18/492,544 is a continuation of application No. 18/168,346, filed on Feb. 13, 2023, granted, now 11,831,280.
Application 18/168,346 is a continuation of application No. 17/189,141, filed on Mar. 1, 2021, granted, now 11,606,067, issued on Mar. 14, 2023.
Prior Publication US 2024/0113665 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 1/22 (2006.01); H03F 3/193 (2006.01); H03F 3/21 (2006.01)
CPC H03F 1/223 (2013.01) [H03F 3/193 (2013.01); H03F 3/21 (2013.01); H03F 2200/294 (2013.01); H03F 2203/7236 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method for turning OFF a branch of a multi-branch cascode amplifier, the method comprising:
i) turning ON a plurality of branches of the multi-branch cascode amplifier by:
providing to each branch of the plurality of branches respective gate biasing voltages to transistors of the branch for operation of the branch as an amplifier during a respective ON state of the branch, the transistors of the branch comprising a common-source input transistor and one or more common-gate cascode transistors; and
based on the providing, outputting an amplified signal at a common output node of the multi-branch cascode amplifier; and
ii) turning OFF at least one branch of the plurality of branches by:
decoupling the at least one branch from the common output node via a first switching arrangement, thereby obtaining a decoupled branch, and
coupling a reference voltage to a drain node of an output transistor of the decoupled branch via a second switching arrangement, thereby maintaining operation of the transistors of the decoupled branch within their respective maximum tolerable voltages.